Designed an IEEE 754 Double-precision Floating Point Multiplier using Verilog.
Completed the Synthesis, APR process and conducted DRC/LVS verification.

Developed a highly modular Rule110, ensuring flexibility and scalability.
Implemented a FSM to control the computational flow and timing.

Designed and implemented a 4-bit ALU circuit with 16 arithmetic functions.
Wrote SDC file, optimize layout parameters, and passed lint and DRC checks.

Implemented a fixed-point FIR filter circuit in an Linear Time-Invariant system.
Combined shift registers, multipliers, and adders to realize high-pass and low-pass filters.

Practiced a total of 182 Verilog exercises on the HDLBits website.
Continuously improved circuit design skills and shared my practice results on GitHub.

Developed a simplified block-pushing game using FPGA(Altera DE2-70).
A demonstration video showcasing the actual gameplay is available on YouTube.

A step-by-step tutorial on installing the Vivado 2023.1 version on Windows, guiding through software download, installation, license application and certification.