Hi, I'm anlit75

TeX ccu ccu-thesis dissertations doctoral-dissertation latex latex-template master-thesis national-chung-cheng-university thesis-latex-template

Verilog adpll ams dco frequency-divider pfd phase-locked-loop

Python gallery profile profile-website showcase showcase-website website

SystemVerilog lab-guide systemverilog-test-bench testbench

Python

Verilog beginner-friendly combinational-circuit sequential-circuits verilog-practice

Python gds rtl rtl-to-gdsii

Verilog

Python gdsii ic-design openlane pnr rtl silicon verilator verilog yosys

ic-design interview-questions

JavaScript