Summary
Files: metrics.json 17.5 kB · history.json 1.6 kB
Tests: 6/6 on RTL, 6/6 on gates
The same cocotb tests, on the RTL and on the synthesized netlist with the PDK cell models.
Seeds: RTL 1791694078 · gates 1791694402. Each seed reruns its run exactly.
| test | RTL | gates |
|---|---|---|
reset_ | PASS | PASS |
register_ | PASS | PASS |
idle_ | PASS | PASS |
loopback | PASS | PASS |
random_ | PASS | PASS |
burst | PASS | PASS |
History (3 commits)
- passed
- total
- passed
- total
Files: cocotb-results.xml 1.3 kB · cocotb-gl-results.xml 1.3 kB
Regression: 12/12 runs passed
Each row is a module of the test list, run once for each of its seeds. Under it are the tests it holds.
Base seed 19193966. make regress SEED=19193966 reruns the list with the same seeds.
| module and its tests | seeds | runs passed |
|---|---|---|
test_
| 10 | 10/10 |
test_
| 1 | 1/1 |
test_
| 1 | 1/1 |
History (3 commits)
- passed
- total
Files: regress-summary.json 1.3 kB
Coverage
Code coverage of the RTL, from the 12 runs of Regression, run again under Verilator and merged.
| kind | covered | share | |
|---|---|---|---|
| Block | 80 / 101 | 79.2% | |
| Branch | 92 / 126 | 73.0% | |
| Toggle | 584 / 958 | 61.0% |
Not measured: expression and FSM coverage. The Verilator in the image does not support them.
Coverage by module (6)
| module | block | branch | toggle |
|---|---|---|---|
apb_uart_sv | 86.7% | 77.8% | 35.0% |
io_generic_fifo__D8_B10 | 100.0% | 100.0% | 83.2% |
io_generic_fifo__D9_B10 | 100.0% | 100.0% | 73.6% |
uart_interrupt__T10_R10 | 50.0% | 50.0% | 52.6% |
uart_rx | 75.8% | 65.6% | 68.1% |
uart_tx | 73.7% | 70.6% | 67.8% |
History (3 commits)
- Block
- Branch
- Toggle
Files: coverage-summary.json 9.8 kB
Timing
Timing is met: no setup or hold slack is negative.
Worst slack after routing, over every corner the flow analysed.
| check | worst slack | violations | reg-to-reg |
|---|---|---|---|
| setup | +2.57 ns | 0 | +2.74 ns |
| hold | +0.04 ns | 0 | +0.11 ns |
Slew, capacitance and fanout limits
Design rule violations after routing, against the limits in the run's constraints. They are warnings: the flow does not stop on them, and the timing verdict above leaves them out.
| limit | violations | corners |
|---|---|---|
| max slew | 9 | max_ss_100C_1v60, nom_ss_100C_1v60 |
| max capacitance | 0 | none |
| max fanout | 10 | max_ff_n40C_1v95, max_ss_100C_1v60, max_tt_025C_1v80, min_ff_n40C_1v95, min_ss_100C_1v60, min_tt_025C_1v80, nom_ff_n40C_1v95, nom_ss_100C_1v60, nom_tt_025C_1v80 |
Constraints the run used (5)
From the post-route timing step. The slack above holds only for these values.
| constraint | value | source |
|---|---|---|
| clock period | 11 ns (91 MHz) | set in config.yaml |
| clock uncertainty | 0.25 ns | flow default |
| clock transition | 0.15 ns | flow default |
| timing derate | 5% | flow default |
| input and output delay | 5% of the clock period (0.55 ns) | set in config.yaml |
History (3 commits)
Files: apb_uart_sv.sdc 17.2 kB
Area and Instances
Standard cell library sky130_fd_sc_hd, single threshold voltage.
Synthesis produced 20,352.0 µm² of instances. Place and route grew it by 26% to 25,629.6 µm².
- flip-flops 10,405.0 µm²
- combinational logic 9,947.0 µm²
- added or resized by place and route 5,277.6 µm²
Instances: 1,411 after synthesis, 2,978 after routing
Placed instances, by LibreLane class. Fill is not counted.
- from synthesis 1,411 (982 logic, 404 sequential, 25 inverters)
- added by the flow 1,564 (777 timing-repair buffers, 609 of them for hold, 714 well taps, 69 clock buffers, 4 clock inverters)
- other 3 (3 antenna cell)
Drive strength of the instances (6 sizes)
Well taps, decap, fill and antenna diodes have no drive strength and are not counted.
| drive strength | after synthesis | after routing |
|---|---|---|
| X1 | 353 | 961 |
| X2 | 1,058 | 1,198 |
| X4 | 0 | 18 |
| X6 | 0 | 19 |
| X8 | 0 | 56 |
| X16 | 0 | 9 |
| Total | 1,411 | 2,261 |
Place and route added 608 X1, 140 X2, 56 X8, 19 X6, 18 X4 and 9 X16 instances.
History (3 commits)
- flip-flops
- combinational logic
- added by place and route
- from synthesis
- added by the flow
Files: apb_uart_sv.nl.v 460.6 kB
Power
3.448 mW in total at corner nom_tt_025C_1v80 (typical wire RC, typical transistors, 25 °C, 1.80 V), clock 91 MHz. The table is in µW.
Switching activity is OpenSTA's default, 0.1 toggles per clock on data nets. It is not taken from simulation, so this estimates where power goes. It does not measure a workload.
| group | internal | switching | leakage | total | share | |
|---|---|---|---|---|---|---|
| Sequential | 1,558.0 | 123.7 | <0.1 | 1,681.7 | 48.8% | |
| Combinational | 314.1 | 300.5 | <0.1 | 614.6 | 17.8% | |
| Clock | 609.2 | 542.5 | <0.1 | 1,151.7 | 33.4% | |
| Total | 2,481.3 | 966.6 | <0.1 | 3,448.0 | 100.0% |
Static IR drop, worst: 0.52 mV, 0.029% of 1.80 V, from OpenROAD (ir__drop__worst).
History (3 commits)
Signoff checks
The DRC row adds the errors of both tools.
| check | errors | result |
|---|---|---|
| DRC Magic and KLayout | 0 | PASS |
| LVS | 0 | PASS |
| antenna checked by OpenROAD, not by DRC | 0 | PASS |
| XOR Magic GDS against KLayout GDS | 0 | PASS |
Not analysed: electromigration, crosstalk and dynamic IR drop.
How it was built
One picture per stage of the real run, which took 4 min 14 s.
- Synthesisno picture7.8 s
RTL becomes gates; lint and a first timing check
Your Verilog is checked, then turned into logic gates from the Sky130 cell library. There is no layout yet, so this stage has no picture. - Floorplan4.0 s
pick the die size, power grid and tap cells
The die is the outline of the chip. The empty rows are where gates will sit, and the stripes are the metal rails that bring power to them. 
Placement14 sgive every gate a place on the die
Every gate now has a place on the die. The small colored blocks are the cells, packed into the rows.
Clock tree29 sbuild the clock distribution and fix its timing
Extra buffers now carry the clock to every flip-flop at nearly the same moment. They are small cells added among the others.
Routing2 min 15 sdraw the wires; repair antenna violations
Metal wires now connect the gates. The colored lines drawn over the cells are wires on different metal layers.
Finish & GDS26 sfill, extract parasitics, final timing, write the GDS
Filler cells close the gaps between the gates, and timing is measured again from the real wires. The picture is the layout that is written to the GDS file.
Signoff39 sDRC, LVS, antenna, XOR: can it be made?
The checks a fab would run on the finished layout. This is the picture of that layout, the one that is handed over.
Files: floorplan.png 61.7 kB · placement.png 145.6 kB · clock-tree.png 153.9 kB · routing.png 295.1 kB · finish-gds.png 279.4 kB