RepoGallery

Hi, I'm anlit75

This is a collection of my awesome GitHub projects.

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19 3 0
@Evie S.

CCU-Thesis-LaTeX-Template

 Unofficial LaTeX templates for both master's thesis and doctoral dissertations at National Chung Cheng University. 國立中正大學碩博士論文LaTex模板
TeX ccu ccu-thesis dissertations doctoral-dissertation latex latex-template master-thesis national-chung-cheng-university thesis-latex-template
3 4 0

RepoGallery

 Just fork & good to go! A beautiful showcase for all your GitHub repos.
Python gallery profile profile-website showcase showcase-website website
2 3 0
@Evie S.

ADPLL

 All Digital Phase-Locked Loop (ADPLL)
Verilog adpll ams dco frequency-divider pfd phase-locked-loop
1 1 0
@Sarah Dorweiler

SV-TBLab

 SystemVerilog Testbench Workshop Lab
SystemVerilog lab-guide systemverilog-test-bench testbench
1 0 0
@Cristina Gottardi

tt05-rule110

 This project uses Verilog to create a 256-cell Rule 110 cellular automaton, which is a one-dimensional system that evolves according to a simple rule.
Verilog cellular-automaton rule-110 verilog-project
0 0 0
@Nadia Valko

DIC-FAQ

 This repo is awesome! But it doesn't have a description yet.
ic-design interview-questions
0 0 0
@Darran Shen

Formal-Property-Verification

 Frequently used module in Formal Property Verification (FPV).
SystemVerilog formal-verification fpv
0 0 0
@Todd Quackenbush

HDLBits

 Verilog practice and solutions on HDLBits website
Verilog beginner-friendly combinational-circuit sequential-circuits verilog-practice
0 0 0
@Glen Carrie

tt05-4bits-ALU

 This 4-bit ALU (Arithmetic Logic Unit) is a digital computation unit capable of executing 16 different operations.
Verilog alu verilog-project