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國立中正大學碩博士論文 LaTeX 模板 (Unofficial CCU Thesis LaTeX Template)。整合 Docker 與 GitHub Codespaces 提供開箱即用的零配置寫作環境。

TeX ccu ccu-thesis dissertations doctoral-dissertation latex latex-template master-thesis national-chung-cheng-university thesis-latex-template

All Digital Phase-Locked Loop (ADPLL)

Verilog adpll ams dco frequency-divider pfd phase-locked-loop

Just fork & good to go! A beautiful showcase for all your GitHub repos.

Python gallery profile profile-website showcase showcase-website website

SystemVerilog Testbench Workshop Lab

SystemVerilog lab-guide systemverilog-test-bench testbench

@Evie S.

Underlying EDA toolchain engine for the ChipForAll project.

Python gds rtl rtl-to-gdsii

A Zero-Config Starter Kit for Open Source Silicon Design.

Makefile gdsii ic-design openlane pnr rtl silicon verilator verilog yosys

This repo is awesome! But it doesn't have a description yet.

ic-design interview-questions

This repo is awesome! But it doesn't have a description yet.

Python

@Evie S.

Verilog practice and solutions on HDLBits website

Verilog beginner-friendly combinational-circuit sequential-circuits verilog-practice