RepoGallery

Hi, I'm anlit75

This is a collection of my awesome GitHub projects.

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36 10 0
@Darran Shen

CCU-Thesis-LaTeX-Template

 國立中正大學碩博士論文 LaTeX 模板 (Unofficial CCU Thesis LaTeX Template)。整合 Docker 與 GitHub Codespaces 提供開箱即用的零配置寫作環境。
TeX ccu ccu-thesis dissertations doctoral-dissertation latex latex-template master-thesis national-chung-cheng-university thesis-latex-template
27 8 0
@Evie S.

ADPLL

 All Digital Phase-Locked Loop (ADPLL)
Verilog adpll ams dco frequency-divider pfd phase-locked-loop
5 6 0

RepoGallery

 Just fork & good to go! A beautiful showcase for all your GitHub repos.
Python gallery profile profile-website showcase showcase-website website
3 2 0
@Glen Carrie

SV-TBLab

 SystemVerilog Testbench Workshop Lab
SystemVerilog lab-guide systemverilog-test-bench testbench
0 0 0
@Barrett Ward

c4o-core

 Underlying EDA toolchain engine for the ChipForAll project.
Python gds rtl rtl-to-gdsii
0 0 0
@Todd Quackenbush

ChipForAll

 A Zero-Config Starter Kit for Open Source Silicon Design.
Makefile gdsii ic-design openlane pnr rtl silicon verilator verilog yosys
0 0 0
@Alexander Andrews

DIC-FAQ

 This repo is awesome! But it doesn't have a description yet.
ic-design interview-questions
0 0 0
@Bench Accounting

HDLBits

 Verilog practice and solutions on HDLBits website
Verilog beginner-friendly combinational-circuit sequential-circuits verilog-practice