{ "design__lint_error__count": 0, "design__lint_timing_construct__count": 0, "design__lint_warning__count": 0, "design__inferred_latch__count": 0, "design__instance__count": 287, "design__instance__area": 1961.88, "design__instance_unmapped__count": 0, "synthesis__check_error__count": 0, "design__max_slew_violation__count__corner:nom_tt_025C_1v80": 0, "design__max_fanout_violation__count__corner:nom_tt_025C_1v80": 0, "design__max_cap_violation__count__corner:nom_tt_025C_1v80": 0, "power__internal__total": 0.0001365468488074839, "power__switching__total": 3.0266714020399377e-05, "power__leakage__total": 1.4215061350242308e-09, "power__total": 0.00016681499255355448, "clock__skew__worst_hold__corner:nom_tt_025C_1v80": -0.31093747900984536, "clock__skew__worst_setup__corner:nom_tt_025C_1v80": 0.26456138029147575, "timing__hold__ws__corner:nom_tt_025C_1v80": 0.31819692226184854, "timing__setup__ws__corner:nom_tt_025C_1v80": 6.8333092229893, "timing__hold__tns__corner:nom_tt_025C_1v80": 0, "timing__setup__tns__corner:nom_tt_025C_1v80": 0, "timing__hold__wns__corner:nom_tt_025C_1v80": 0, "timing__setup__wns__corner:nom_tt_025C_1v80": 0, "timing__hold_vio__count__corner:nom_tt_025C_1v80": 0, "timing__hold_r2r__ws__corner:nom_tt_025C_1v80": 0.318197, "timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80": 0, "timing__setup_vio__count__corner:nom_tt_025C_1v80": 0, "timing__setup_r2r__ws__corner:nom_tt_025C_1v80": 8.145524, "timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80": 0, "design__max_slew_violation__count__corner:nom_ss_100C_1v60": 0, "design__max_fanout_violation__count__corner:nom_ss_100C_1v60": 0, "design__max_cap_violation__count__corner:nom_ss_100C_1v60": 0, "clock__skew__worst_hold__corner:nom_ss_100C_1v60": -0.3554590333798554, "clock__skew__worst_setup__corner:nom_ss_100C_1v60": 0.2749079097730604, "timing__hold__ws__corner:nom_ss_100C_1v60": 0.9018731017267411, "timing__setup__ws__corner:nom_ss_100C_1v60": 5.974008568035413, "timing__hold__tns__corner:nom_ss_100C_1v60": 0, "timing__setup__tns__corner:nom_ss_100C_1v60": 0, "timing__hold__wns__corner:nom_ss_100C_1v60": 0, "timing__setup__wns__corner:nom_ss_100C_1v60": 0, "timing__hold_vio__count__corner:nom_ss_100C_1v60": 0, "timing__hold_r2r__ws__corner:nom_ss_100C_1v60": 0.901873, "timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60": 0, "timing__setup_vio__count__corner:nom_ss_100C_1v60": 0, "timing__setup_r2r__ws__corner:nom_ss_100C_1v60": 6.388361, "timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60": 0, "design__max_slew_violation__count__corner:nom_ff_n40C_1v95": 0, "design__max_fanout_violation__count__corner:nom_ff_n40C_1v95": 0, "design__max_cap_violation__count__corner:nom_ff_n40C_1v95": 0, "clock__skew__worst_hold__corner:nom_ff_n40C_1v95": -0.29221237368020847, "clock__skew__worst_setup__corner:nom_ff_n40C_1v95": 0.26014091617160895, "timing__hold__ws__corner:nom_ff_n40C_1v95": 0.10977979946929117, "timing__setup__ws__corner:nom_ff_n40C_1v95": 7.14882218101321, "timing__hold__tns__corner:nom_ff_n40C_1v95": 0, "timing__setup__tns__corner:nom_ff_n40C_1v95": 0, "timing__hold__wns__corner:nom_ff_n40C_1v95": 0, "timing__setup__wns__corner:nom_ff_n40C_1v95": 0, "timing__hold_vio__count__corner:nom_ff_n40C_1v95": 0, "timing__hold_r2r__ws__corner:nom_ff_n40C_1v95": 0.10978, "timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95": 0, "timing__setup_vio__count__corner:nom_ff_n40C_1v95": 0, "timing__setup_r2r__ws__corner:nom_ff_n40C_1v95": 8.731001, "timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95": 0, "design__max_slew_violation__count": 0, "design__max_fanout_violation__count": 0, "design__max_cap_violation__count": 0, "clock__skew__worst_hold": -0.2915599511013357, "clock__skew__worst_setup": 0.2598821231772497, "timing__hold__ws": 0.10796025490277276, "timing__setup__ws": 5.9639694870736175, "timing__hold__tns": 0, "timing__setup__tns": 0, "timing__hold__wns": 0, "timing__setup__wns": 0, "timing__hold_vio__count": 0, "timing__hold_r2r__ws": 0.10796, "timing__hold_r2r_vio__count": 0, "timing__setup_vio__count": 0, "timing__setup_r2r__ws": 6.37595, "timing__setup_r2r_vio__count": 0, "design__die__bbox": "0.0 0.0 56.375 67.095", "design__core__bbox": "5.52 10.88 50.6 54.4", "design__io": 5, "design__die__area": 3782.48, "design__core__area": 1961.88, "design__instance__count__stdcell": 116, "design__instance__area__stdcell": 1014.72, "design__instance__count__macros": 0, "design__instance__area__macros": 0, "design__instance__count__padcells": 0, "design__instance__area__padcells": 0, "design__instance__count__cover": 0, "design__instance__area__cover": 0, "design__instance__utilization": 0.517219, "design__instance__utilization__stdcell": 0.517219, "design__rows": 16, "design__rows:unithd": 16, "design__sites": 1568, "design__sites:unithd": 1568, "design__instance__count__class:inverter": 17, "design__instance__area__class:inverter": 63.8112, "design__instance__count__class:sequential_cell": 16, "design__instance__area__class:sequential_cell": 420.403, "design__instance__count__class:multi_input_combinational_cell": 32, "design__instance__area__class:multi_input_combinational_cell": 337.824, "flow__warnings__count": 1, "flow__errors__count": 0, "flow__warnings__count:ODB-0220": 2, "flow__warnings__type_count": 1, "flow__warnings__count:ORD-0039": 1, "design__instance__count__class:fill_cell": 171, "design__instance__area__class:fill_cell": 947.158, "design__instance__count__class:tap_cell": 27, "design__instance__area__class:tap_cell": 33.7824, "design__power_grid_violation__count__net:VPWR": 0, "design__power_grid_violation__count__net:VGND": 0, "design__power_grid_violation__count": 0, "floorplan__design__io": 3, "design__io__hpwl": 164523, "timing__drv__floating__nets": 2, "timing__drv__floating__pins": 0, "design__instance__displacement__total": 39.546, "design__instance__displacement__mean": 0.267, "design__instance__displacement__max": 4.303, "route__wirelength__estimated": 1082.55, "design__violations": 0, "design__instance__count__class:timing_repair_buffer": 21, "design__instance__area__class:timing_repair_buffer": 83.8304, "flow__warnings__count:RSZ-0020": 1, "flow__warnings__count:STA-1140": 6, "design__instance__count__class:clock_buffer": 3, "design__instance__area__class:clock_buffer": 75.072, "design__instance__count__setup_buffer": 0, "design__instance__count__hold_buffer": 17, "global_route__vias": 486, "global_route__wirelength": 2125, "antenna__violating__nets": 0, "antenna__violating__pins": 0, "route__antenna_violation__count": 0, "antenna_diodes_count": 0, "route__net": 91, "route__net__special": 2, "route__drc_errors__iter:0": 1, "route__wirelength__iter:0": 1157, "route__drc_errors__iter:1": 0, "route__wirelength__iter:1": 1139, "route__drc_errors": 0, "route__wirelength": 1139, "route__vias": 510, "route__vias__singlecut": 510, "route__vias__multicut": 0, "flow__warnings__count:DRT-0349": 10, "design__disconnected_pin__count": 0, "design__critical_disconnected_pin__count": 0, "route__wirelength__max": 118.64, "timing__unannotated_net__count__corner:nom_tt_025C_1v80": 0, "timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80": 0, "timing__unannotated_net__count__corner:nom_ss_100C_1v60": 0, "timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60": 0, "timing__unannotated_net__count__corner:nom_ff_n40C_1v95": 0, "timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95": 0, "design__max_slew_violation__count__corner:min_tt_025C_1v80": 0, "design__max_fanout_violation__count__corner:min_tt_025C_1v80": 0, "design__max_cap_violation__count__corner:min_tt_025C_1v80": 0, "clock__skew__worst_hold__corner:min_tt_025C_1v80": -0.31011927237313175, "clock__skew__worst_setup__corner:min_tt_025C_1v80": 0.2642491023013925, "timing__hold__ws__corner:min_tt_025C_1v80": 0.31457209949508164, "timing__setup__ws__corner:min_tt_025C_1v80": 6.838066306739753, "timing__hold__tns__corner:min_tt_025C_1v80": 0, "timing__setup__tns__corner:min_tt_025C_1v80": 0, "timing__hold__wns__corner:min_tt_025C_1v80": 0, "timing__setup__wns__corner:min_tt_025C_1v80": 0, "timing__hold_vio__count__corner:min_tt_025C_1v80": 0, "timing__hold_r2r__ws__corner:min_tt_025C_1v80": 0.314572, "timing__hold_r2r_vio__count__corner:min_tt_025C_1v80": 0, "timing__setup_vio__count__corner:min_tt_025C_1v80": 0, "timing__setup_r2r__ws__corner:min_tt_025C_1v80": 8.152087, "timing__setup_r2r_vio__count__corner:min_tt_025C_1v80": 0, "timing__unannotated_net__count__corner:min_tt_025C_1v80": 0, "timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80": 0, "design__max_slew_violation__count__corner:min_ss_100C_1v60": 0, "design__max_fanout_violation__count__corner:min_ss_100C_1v60": 0, "design__max_cap_violation__count__corner:min_ss_100C_1v60": 0, "clock__skew__worst_hold__corner:min_ss_100C_1v60": -0.35426648728422677, "clock__skew__worst_setup__corner:min_ss_100C_1v60": 0.27450648087157836, "timing__hold__ws__corner:min_ss_100C_1v60": 0.8973241847992922, "timing__setup__ws__corner:min_ss_100C_1v60": 5.9819413338153185, "timing__hold__tns__corner:min_ss_100C_1v60": 0, "timing__setup__tns__corner:min_ss_100C_1v60": 0, "timing__hold__wns__corner:min_ss_100C_1v60": 0, "timing__setup__wns__corner:min_ss_100C_1v60": 0, "timing__hold_vio__count__corner:min_ss_100C_1v60": 0, "timing__hold_r2r__ws__corner:min_ss_100C_1v60": 0.897324, "timing__hold_r2r_vio__count__corner:min_ss_100C_1v60": 0, "timing__setup_vio__count__corner:min_ss_100C_1v60": 0, "timing__setup_r2r__ws__corner:min_ss_100C_1v60": 6.399796, "timing__setup_r2r_vio__count__corner:min_ss_100C_1v60": 0, "timing__unannotated_net__count__corner:min_ss_100C_1v60": 0, "timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60": 0, "design__max_slew_violation__count__corner:min_ff_n40C_1v95": 0, "design__max_fanout_violation__count__corner:min_ff_n40C_1v95": 0, "design__max_cap_violation__count__corner:min_ff_n40C_1v95": 0, "clock__skew__worst_hold__corner:min_ff_n40C_1v95": -0.2915599511013357, "clock__skew__worst_setup__corner:min_ff_n40C_1v95": 0.2598821231772497, "timing__hold__ws__corner:min_ff_n40C_1v95": 0.10796025490277276, "timing__setup__ws__corner:min_ff_n40C_1v95": 7.152360683937371, "timing__hold__tns__corner:min_ff_n40C_1v95": 0, "timing__setup__tns__corner:min_ff_n40C_1v95": 0, "timing__hold__wns__corner:min_ff_n40C_1v95": 0, "timing__setup__wns__corner:min_ff_n40C_1v95": 0, "timing__hold_vio__count__corner:min_ff_n40C_1v95": 0, "timing__hold_r2r__ws__corner:min_ff_n40C_1v95": 0.10796, "timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95": 0, "timing__setup_vio__count__corner:min_ff_n40C_1v95": 0, "timing__setup_r2r__ws__corner:min_ff_n40C_1v95": 8.735565, "timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95": 0, "timing__unannotated_net__count__corner:min_ff_n40C_1v95": 0, "timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95": 0, "design__max_slew_violation__count__corner:max_tt_025C_1v80": 0, "design__max_fanout_violation__count__corner:max_tt_025C_1v80": 0, "design__max_cap_violation__count__corner:max_tt_025C_1v80": 0, "clock__skew__worst_hold__corner:max_tt_025C_1v80": -0.3121465396734323, "clock__skew__worst_setup__corner:max_tt_025C_1v80": 0.2650963412710211, "timing__hold__ws__corner:max_tt_025C_1v80": 0.3220554469819086, "timing__setup__ws__corner:max_tt_025C_1v80": 6.8275165231721875, "timing__hold__tns__corner:max_tt_025C_1v80": 0, "timing__setup__tns__corner:max_tt_025C_1v80": 0, "timing__hold__wns__corner:max_tt_025C_1v80": 0, "timing__setup__wns__corner:max_tt_025C_1v80": 0, "timing__hold_vio__count__corner:max_tt_025C_1v80": 0, "timing__hold_r2r__ws__corner:max_tt_025C_1v80": 0.322055, "timing__hold_r2r_vio__count__corner:max_tt_025C_1v80": 0, "timing__setup_vio__count__corner:max_tt_025C_1v80": 0, "timing__setup_r2r__ws__corner:max_tt_025C_1v80": 8.138335, "timing__setup_r2r_vio__count__corner:max_tt_025C_1v80": 0, "timing__unannotated_net__count__corner:max_tt_025C_1v80": 0, "timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80": 0, "design__max_slew_violation__count__corner:max_ss_100C_1v60": 0, "design__max_fanout_violation__count__corner:max_ss_100C_1v60": 0, "design__max_cap_violation__count__corner:max_ss_100C_1v60": 0, "clock__skew__worst_hold__corner:max_ss_100C_1v60": -0.3570911167833641, "clock__skew__worst_setup__corner:max_ss_100C_1v60": 0.2755311057299833, "timing__hold__ws__corner:max_ss_100C_1v60": 0.9076207819989321, "timing__setup__ws__corner:max_ss_100C_1v60": 5.9639694870736175, "timing__hold__tns__corner:max_ss_100C_1v60": 0, "timing__setup__tns__corner:max_ss_100C_1v60": 0, "timing__hold__wns__corner:max_ss_100C_1v60": 0, "timing__setup__wns__corner:max_ss_100C_1v60": 0, "timing__hold_vio__count__corner:max_ss_100C_1v60": 0, "timing__hold_r2r__ws__corner:max_ss_100C_1v60": 0.907621, "timing__hold_r2r_vio__count__corner:max_ss_100C_1v60": 0, "timing__setup_vio__count__corner:max_ss_100C_1v60": 0, "timing__setup_r2r__ws__corner:max_ss_100C_1v60": 6.37595, "timing__setup_r2r_vio__count__corner:max_ss_100C_1v60": 0, "timing__unannotated_net__count__corner:max_ss_100C_1v60": 0, "timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60": 0, "design__max_slew_violation__count__corner:max_ff_n40C_1v95": 0, "design__max_fanout_violation__count__corner:max_ff_n40C_1v95": 0, "design__max_cap_violation__count__corner:max_ff_n40C_1v95": 0, "clock__skew__worst_hold__corner:max_ff_n40C_1v95": -0.2932362491380506, "clock__skew__worst_setup__corner:max_ff_n40C_1v95": 0.2606016032287063, "timing__hold__ws__corner:max_ff_n40C_1v95": 0.11126994085508714, "timing__setup__ws__corner:max_ff_n40C_1v95": 7.144284033249404, "timing__hold__tns__corner:max_ff_n40C_1v95": 0, "timing__setup__tns__corner:max_ff_n40C_1v95": 0, "timing__hold__wns__corner:max_ff_n40C_1v95": 0, "timing__setup__wns__corner:max_ff_n40C_1v95": 0, "timing__hold_vio__count__corner:max_ff_n40C_1v95": 0, "timing__hold_r2r__ws__corner:max_ff_n40C_1v95": 0.11127, "timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95": 0, "timing__setup_vio__count__corner:max_ff_n40C_1v95": 0, "timing__setup_r2r__ws__corner:max_ff_n40C_1v95": 8.725856, "timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95": 0, "timing__unannotated_net__count__corner:max_ff_n40C_1v95": 0, "timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95": 0, "timing__unannotated_net__count": 0, "timing__unannotated_net_filtered__count": 0, "design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80": 1.79982, "design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80": 1.79997, "design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80": 0.000177202, "design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80": 0.000194925, "design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80": 2.84832e-05, "design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80": 0.000194925, "design_powergrid__voltage__worst": 0.000194925, "design_powergrid__voltage__worst__net:VPWR": 1.79982, "design_powergrid__drop__worst": 0.000194925, "design_powergrid__drop__worst__net:VPWR": 0.000177202, "design_powergrid__voltage__worst__net:VGND": 0.000194925, "design_powergrid__drop__worst__net:VGND": 0.000194925, "ir__voltage__worst": 1.8, "ir__drop__avg": 3.33e-05, "ir__drop__worst": 0.000177, "design__xor_difference__count": 0, "magic__drc_error__count": 0, "klayout__drc_error__count": 0, "magic__illegal_overlap__count": 0, "design__lvs_device_difference__count": 0, "design__lvs_net_difference__count": 0, "design__lvs_property_fail__count": 0, "design__lvs_error__count": 0, "design__lvs_unmatched_device__count": 0, "design__lvs_unmatched_net__count": 0, "design__lvs_unmatched_pin__count": 0 }